The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 08, 2004
Filed:
Mar. 18, 2003
Yasuaki Ishikawa, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A power-on reset circuit has a configuration comprising an input circuit which is initialized by the assertion of a power-on reset signal entered from outside when power supply is turned on and supplies a first signal of a first logical value at the time a detection signal is entered, a reset extending circuit which is initialized by the assertion of the power-on reset signal and, after the power-on reset signal is negated, supplies a second signal which takes on a second logical value when an external clock signal is first entered and a third logical value after the lapse of a prescribed length of time determined by counting the external clock signals after the first signal of the first logical value is entered, a detecting circuit which is initialized by the assertion of the power-on reset signal and, after the power-on reset signal is negated, caused to generate the detection signal by the input of the second signal of the second logical value from the reset extending circuit and to supply it to the input circuit, and a gate circuit which supplies a reset signal of a prescribed logical value when the first signal of the first logical value is supplied from the input circuit and the second signal of the third logical value is supplied from the reset extending circuit.