Sense amplifier type input receiver with improved clk to q

Abstract

A sense amplifier type input receiver includes a differential receiver circuit operatively coupled to an output stage. The output stage includes a pass gate enabled latch. The differential receiver circuit may output a first differential output and a second differential output. The output stage may include a first pass gate operatively coupled between the first differential output and an output of the output stage, a second pass gate operatively coupled between the second differential output and the pass gate enabled latch, and the pass gate enabled latch may be operatively coupled to the output of the output stage. A first clock signal and second clock signal may be coupled to the first pass gate to enable passing of the first differential output to the output of the output stage, the first and second clock signals may be coupled to the second pass gate to enable passing of the second differential output to the pass gate enabled latch, and the first and second clocks signal coupled to a pass gate of the pass gate enabled latch to enable operation of the pass gate enabled latch. A first inverter may be operatively coupled between the first differential output and the first pass gate, a second inverter operatively coupled between the second differential output and the second pass gate, and a third inverter operatively coupled to the output of the output stage.