The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 08, 2004

Filed:

May. 21, 2002
Applicant:
Inventors:

Junichi Karasawa, Tatsuno-machi, JP;

Kunio Watanabe, Sakata, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ; G11C 1/100 ;
U.S. Cl.
CPC ...
H01L 2/976 ; H01L 2/994 ; H01L 3/1062 ; H01L 3/1113 ; H01L 3/1119 ; G11C 1/100 ;
Abstract

A semiconductor device having a memory cell including first and second load transistors, first and second driver transistors, and first and second transfer transistors. The semiconductor device includes first and second gate—gate electrode layers, first and second drain—drain wiring layers, and first and second drain-gate wiring layers. The first drain-gate wiring layer and the second drain-gate wiring layer are located in different layers. The first drain-gate wiring layer is located below the first drain—drain wiring layer, and the second drain-gate wiring layer is located in above the first drain—drain wiring layer. This structure provides a semiconductor device that has reduced cell area. The invention also provides a memory system and electronic apparatus that include the above semiconductor device.


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