The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 01, 2004

Filed:

Feb. 15, 2001
Applicant:
Inventor:

Paul Wong, San Jose, CA (US);

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 3/128 ;
U.S. Cl.
CPC ...
G01R 3/128 ;
Abstract

The present invention relates to an improved digital circuit design employing scannable state elements. In one embodiment, a digital circuit design includes a first functional latch coupled to a first logic block and a second functional latch coupled to a second logic block. The functional latches are in separate scan chains and receive their own respective scan in inputs. The functional latches are both coupled to a common holding latch that captures content from the functional latches. In another embodiment, the digital circuit design includes two logic blocks that are coupled to a scannable state element. The functional latch is disposed within two different scan chains and receives scan in inputs from both scan chains. The functional latch may test the first and second logic blocks to provide controllability and observability. By sharing a common scannable state element, the invention reduces overhead and space in the circuit design.


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