Method and system for bypassing memory controller components

Abstract

A method and system are shown for bypassing memory controller components when processing memory requests. A memory controller analyzes internal components to determine if any pending memory requests exist. If particular memory controller components are idle, a memory client is informed that a bypassing of memory controller components is possible. A bypass module of the memory controller receives memory requests from the memory client. The bypass module examines memory controller parameters and a configuration of main memory to determine which memory controller components may be bypassed and routes the memory request accordingly. In a system with asynchronous memory, the memory controller provides copies of the memory request through a dual pipeline. A first copy of the memory request is processed through a bypass module to attempt to bypass memory controller components. A second copy of the memory request is processed in a normal fashion in case a bypass of the memory access request is not possible. If the bypass is possible, the second memory request is cancelled.