The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 01, 2004
Filed:
Oct. 04, 2002
Applicant:
Inventor:
Paul H. Kydd, Lawrenceville, NJ (US);
Assignee:
Paralec Inc., Rocky Hill, NJ (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B65C 1/165 ; B32B 3/120 ; B32B 3/300 ; B05D 5/12 ; H05K 1/09 ;
U.S. Cl.
CPC ...
B65C 1/165 ; B32B 3/120 ; B32B 3/300 ; B05D 5/12 ; H05K 1/09 ;
Abstract
An electronic circuit is made by printing a Parmod® composition on a temporary substrate and curing it to produce a pattern of metal conductors. The conductors are laminated to a substrate under heat and pressure to produce a laminate with the metal prepatterned into the desired circuit configuration. The conductor can also be coated with a polymer and cured to form a prepatterned substrate. Single and double-sided circuits or multilayers can be made this way.
Kydd, Paul. (2004). Adhesiveless transfer lamination method and materials for producing electronic circuits (U.S. Patent No. 6743319). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6743319
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile