The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6742159 B1

PDF
Full Text
Expired
Date of Patent:
May. 25, 2004

Filed:

Jan. 22, 2001
Applicant:
Inventor:

Yasutomo Sakurai, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/100 ; G11C 2/900 ;
U.S. Cl.
CPC ...
G06F 1/100 ; G11C 2/900 ;
Abstract

To improve the processing efficiency and throughput by performing only a recovery process in read-accessing to a memory even when an address parity error has occurred in write-accessing to the memory, a selector is provided to select one of write data and a parity-bitted address for writing to the memory. If an address parity error has detected, the selector selects the parity-bitted address, in which the address parity error has occurred, instead of write data to be written to the memory during the write-accessing thereto. This address parity error processing method is particularly useful when applied to an information processor, such as a computer system, including a storage (memory).


Find Patent Forward Citations

Sakurai, Yasutomo. (2004). Address parity error processing method, and apparatus and storage for the method (U.S. Patent No. 6742159). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6742159

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