Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution

Abstract

A processing engine for executing instructions in parallel comprises an instruction buffer for holding at least two instructions, with the first instruction in a first position and the second instruction in a second position. A first decoder provides decoding of the first instruction and generates first control signals. The first control signals include first resource control signals, first address generation control signals, and a first validity signal indicative of the validity of the first instruction in the first position. A second decoder provides decoding of the second instruction and generates second control signals. The second control signals include second resource control signals, second address generation control signals, and a second validity signal indicative of the validity of the second instruction in the second position. Arbitration and merge logic is provided for arbitrating between the first and second control signals and for merging the first and second control signals for controlling power of execution of the instructions in accordance with a set of parallelism rules. A conditional execution unit is responsive to false condition signals from the arbitration and merge logic to inhibit or modify the effect of the control signals. The parallelism rules provide for efficient instruction execution, and the avoidance of resource conflicts.