The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6742102 B1

PDF
Full Text
Expired
Date of Patent:
May. 25, 2004

Filed:

Mar. 28, 2001
Applicant:
Inventor:

Masashi Sasahara, Kawasaki, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/208 ;
U.S. Cl.
CPC ...
G06F 1/208 ;
Abstract

A microprocessor capable of suppressing reduction in performance caused due to a cache miss when a specific command is issued. The processor according to the present invention comprises a command buffer/queue; an execution unit; a subroutine call decoder; a data cache control unit; an Addiu decoder for detecting an addiu command; a pre-fetch control section; an adder; a PAdr register; a selector; and an adder circuit. When a subroutine call occurs, a stack pointer is moved by an amount used in a subroutine, and data used in the subroutine is pre-fetched to be stored in an area used by the subroutine in a data cache. Therefore, it is possible to reduce cache miss penalties due to stack access which is apt to be generated at the time of a subroutine call.


Find Patent Forward Citations

Sasahara, Masashi. (2004). Microprocessor and cache controlling method (U.S. Patent No. 6742102). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6742102

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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