Data register for buffering double-data-rate drams with reduced data-input-path power consumption

Abstract

A buffer chip clocks data to memories on a memory module. The data-input path to registers or flip-flops on the buffer chip are speeded up by removing muxes on the inputs to the flip-flops. Speeding up the data-input path allows power dissipation to be reduced, since smaller input buffers can be used. Control logic combines chip-select and data-strobe control inputs that prevent clocking of the flip-flops. The control logic outputs a combined strobe signal. Set-reset latches are triggered by the combined strobe signal. The set-reset latches allow the clock to pass through to the flip-flop when the chip-select and data-strobe inputs are both active. The set-reset latches block a rising transition of chip-select and data-strobe inputs from changing the clocks to the flip-flop, thus preventing data-clocking errors.