The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2004

Filed:

Apr. 18, 2003
Applicant:
Inventors:

Katsuyuki Yasukouchi, Kasugai, JP;

Ayuko Watabe, Kasugai, JP;

Katsuya Shimizu, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 2/702 ;
U.S. Cl.
CPC ...
G11C 2/702 ;
Abstract

A peak hold circuit which improves the precision of a hold voltage. The peak hold circuit includes a first input transistor which receives an input voltage and a second input transistor which receives the hold voltage. The peak hold circuit further includes a hold capacitor, a hold-voltage setting transistor and a bypass circuit. The hold capacitor supplies the hold voltage to the second input transistor. The hold-voltage setting transistor receives base current from the collector of the first input transistor and makes the hold voltage coincide with the input voltage in accordance with the base current. The bypass circuit bypasses bias current to be supplied to the second input transistor when the hold-voltage setting transistor is turned off.


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