The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2004

Filed:

Oct. 04, 2002
Applicant:
Inventor:

Kazuhisa Sakamoto, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/974 ;
U.S. Cl.
CPC ...
H01L 2/974 ;
Abstract

A junction field-effect transistor is formed by providing a p-type gate region in a surface of an n-type semiconductor layer and n-type drain and source regions sandwiching the gate region on the surface of the n-type semiconductor layer. A p-type diffusion region is formed at least in the region on the side of the drain close to the gate region on the surface of the n-type semiconductor layer. A drain electrode is formed so that it contacts with the p-type diffusion region. As a result, the junction FET can be reduced in drain-source leak current I to a small, stable value. Thus, a high-gain junction field-effect transistor is obtained which has small variation in performance among actual units manufactured.


Find Patent Forward Citations

Sakamoto, Kazuhisa. (2004). Junction field-effect transistor (U.S. Patent No. 6740907). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6740907

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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