The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2004

Filed:

Mar. 20, 2001
Applicant:
Inventors:

Tinchee Lo, Fishkill, NY (US);

John D. Flanagan, Rhinebeck, NY (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/04 ; G06F 1/06 ; G06F 1/08 ;
U.S. Cl.
CPC ...
G06F 1/04 ; G06F 1/06 ; G06F 1/08 ;
Abstract

A clock controller and clock generating method are provided for AC self-test timing analysis of a logic system. The controller includes latch circuitry which receives a DC input signal at a data input, and a pair of continuous out-of-phase clock signals at capture and launch clock inputs thereof. The latch circuitry outputs two overlapping pulses responsive to the DC input signal going high. The two overlapping pulses are provided to waveform shaper circuitry which produces therefrom two non-overlapping pulses at clock speed of the logic system to be tested. The two non-overlapping pulses are a single pair of clock pulses which facilitate AC self-test timing analysis of the logic system.


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