Cache memory device including word line driver circuit and method

Abstract

A cache memory device and method are provided with a word line driver circuit that can increase the operational speed of the cache memory device and yield a reduction in the chip area of a semiconductor integrated circuit, where a cache memory device includes a first memory cell block, a second memory cell block, a plurality of first content addressable memory (“CAM”) cells, a plurality of second CAM cells, a first word line driver circuit, and a second word line driver circuit; and a corresponding method provides that the plurality of first content addressable memory (“CAM”) cells stores a tag address of the first memory cell block commonly connected to a first dynamic node, and the plurality of second CAM cells stores a tag address of the second memory cell block commonly connected to a second dynamic node; the first and second dynamic nodes are initially precharged to a predetermined level; the precharged predetermined level of one of the first and second dynamic nodes is maintained and the other one is discharged when an address is input from a CPU; and in particular, the first word line driver circuit activates the word line of the first memory cell block when the predetermined level of the first dynamic node is maintained and the second dynamic node is discharged, and the second word line driver circuit activates the word line of the second memory cell block when the predetermined level of the second dynamic node is maintained and the first dynamic node is discharged.