The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2004

Filed:

Feb. 23, 2001
Applicant:
Inventor:

Douglas Sudjian, Santa Clara, CA (US);

Assignee:

Resonext Communications, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/356 ;
U.S. Cl.
CPC ...
H03K 3/356 ;
Abstract

Techniques to improve the operating speed and switching performance of a latch having an integrated gate. In one design, the latch includes first and second differential amplifiers and a feedback circuit (e.g., a third differential amplifier). The first differential amplifier has a number of non-inverting inputs (e.g., configured to implement an OR function) and an inverting input, receives and senses input signals applied to the non-inverting inputs during a “sensing” phase, and provides a differential output. The second differential amplifier latches the output during a “latching” phase. The feedback circuit detects the non-inverting output and provides a control signal for the inverting input of the first differential amplifier. The feedback circuit can provide positive feedback, and can dynamically adjust the inverting input to provide improved switching performance. A fourth differential amplifier receives a differential clock signal, and activates the first and second differential amplifiers during the sensing and latching phases, respectively.


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