The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 18, 2004

Filed:

Jul. 30, 2002
Applicant:
Inventors:

Haruhiko Shigemasa, Yamatokoriyama, JP;

Yoshihiro Nakao, Ikoma, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 ;
U.S. Cl.
CPC ...
H03L 7/00 ;
Abstract

A power-on reset circuit includes a first reset circuit, a second reset circuit, and an NOR circuit. The first reset circuit detects VCC V supplied to a logic section so as to produce a first reset signal RST and the second reset circuit detects REGIN voltage, which is an output voltage of a rectifying circuit that rectifies power voltage obtained from an external power supply source, so as to produce a second reset signal RST The NOR circuit outputs either the RST or the RST as a reset signal P-RST. The above arrangement can provide the power-on reset circuit which outputs a reliable and effective reset signal even in case where the rising of power obtained from the external power supply source varies.


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