System for suspending current bus cycle of microprocessor upon receiving external bus retry signal for executing other process and re-staring the suspended bus cycle thereafter

Abstract

The present invention is directed to a microprocessor (MPU) 10 comprising a bridge chip including a bus retry output part ( ) for outputting a bus retry (BRTY) signal; a bus retry detection part ( ) for determining whether a bus retry signal is input from the bridge chip ; and a bus cycle controller ( ) for suspending a currently executed bus cycle in response to detection of the bus retry signal and for re-starting the suspended bus cycle. The bridge chip also preferably includes an interrupt detection part ( ) for determining whether another process request is issued during suspension of the bus cycle; and an interrupt controller ( ) for executing that other process before re-starting the suspended bus cycle.