The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2004

Filed:

May. 15, 2001
Applicant:
Inventors:

Daisuke Terasawa, San Diego, CA (US);

Avneesh Agrawal, San Jose, CA (US);

Sivarama Venkatesan, Eatontown, NJ (US);

Assignee:

Qualcomm Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/02 ;
U.S. Cl.
CPC ...
G06F 1/02 ;
Abstract

Techniques for fast-slewing of multi-sequence based PN generators are disclosed. In one aspect, LFSR states and reference counter states are loaded into their corresponding components such that consistency among the states is maintained. In another aspect, various methods for determining LFSR states and counter values in response to a desired offset in a unique code are disclosed. Among these methods are matrix-multiplication of LFSR states and generation of advanced LFSR states through masking techniques. Other methods are also presented. These aspects have the benefit of decreasing slew time in an efficient manner, which translates to increased acquisition speed, faster finger lock on multi-path signals, increased data throughput, decreased power, and improved overall system capacity.


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