The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2004
Filed:
Nov. 29, 2001
Steven Michael Douskey, Rochester, MN (US);
Daniel Mark Dreps, Georgetown, TX (US);
Frank David Ferraiolo, Essex Junction, VT (US);
Curtis Walter Preuss, Rochester, MN (US);
Robert James Reese, Austin, TX (US);
Paul William Rudrud, Rochester, MN (US);
James Donald Ryan, Rochester, MN (US);
Robert Russell Williams, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An inter-chip line transmission circuit in a transmitting chip and complementary receiving circuit in a receiving chip provide the capability to characterize the inter-chip interface by separately generating identical pseudo-random test data at both chips, comparing the data, and recording errors. Preferably, one or both chips can be tuned on an individual line basis to reduce errors by altering threshold detection voltage, signal delay, and/or driver power. The receiver circuit preferably contains counters for counting test cycles and errors, which can be masked for any particular line or type of error. A tunable and characterizable interface in accordance with the preferred embodiment thus supports the accurate determination of low error rates on an individual line basis for various tuning parameter settings.