The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 11, 2004
Filed:
Oct. 12, 2001
Ashok Kumar Anand, Schenectady, NY (US);
Brian Jacob Berry, Troy, NY (US);
Johnny Yit Boey, Clifton Park, NY (US);
Michael Jandrisevits, Clifton Park, NY (US);
Patrick King Wah May, Schenectady, NY (US);
Gregory Paul Wotzak, Schenectady, NY (US);
General Electric Company, Schenectady, NY (US);
Abstract
A system and method for analyzing a design using predetermined analysis models are presented. The method may be carried out on an automated design system including an integration server in communication with a plurality of subprocess servers each configured for conducting a subprocess analysis using one of the analysis models. The method comprises receiving at the integration server an analysis request including a set of desired performance parameters and constructing a set of design characteristics for meeting the desired performance parameters. The method further includes determining a set of design performance results associated with the set of design characteristics using the analysis models of the subprocess servers. The step of determining may include passing input information from the integration server to the plurality of subprocess servers, at least a portion of the input information being respectively processed to a format usable in the analysis model of each of the plurality of subprocess servers, passing output information from each of the plurality of subprocess servers to the integration server and using the output information to determine the design performance results.