The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2004

Filed:

Oct. 01, 2002
Applicant:
Inventor:

Seung Cheol Oh, San Jose, CA (US);

Assignee:

Nanoamp Solutions, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A power-up control circuit has three components including a normal power-supply voltage level detection section, a special command section for detecting a deep-sleep enable input signal, and an output driver section that logically combines the output signal of the normal power-supply voltage level detection section and the special command detecting section to provide an improved, combined power-up control signal CPWRUP. The combined power-up control signal CPWRUP signal is temporarily brought to a LOW state for a predetermined period of time immediately after the end of a power-saving mode of operation, such as a deep-sleep mode of operation for a memory device. The LOW state of the combined power-up control signal CPWRUP output signal allows all internal circuitry to be returned to their initial states that are the same as those obtained after a normal power-up sequence, even though the external voltage level stays at its normal level.


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