Data input circuit for reducing loading difference between fetch signal and multiple data in semiconductor device

Abstract

A data input circuit for use in a semiconductor device, the data input circuit reducing a load difference between a fetch signal and a plurality of groups of data. The data input circuit includes first through N latching units for latching each one of N groups of data in response to a reference clock, respectively (N is a natural number greater than 2), and a bus for transmitting the reference clock and the N groups of data to the first through N latching units. Each of the first through N latching units includes a clock buffer for buffering the reference clock; a data buffer for buffering a corresponding group of data of the N groups of data; N−1 dummy elements for respectively receiving each one of the N groups of data, except for the group of data input to the data buffer; and latches for latching data output from the data buffer in synchronization with a signal output from the clock buffer. Use of the data input circuit makes a load on a reference clock the same or substantially the same as that on each group of data. Therefore, a load difference between the reference clock and each group of data is reduced to reduce a skew therebetween.