Self-clocked complementary logic

Abstract

A superconducting self-clocked complementary SFQ logic family. The basic element of the circuit is a plurality of Josephson junctions and a control inductance coupled across a pair of voltage rails. An important aspect of the invention relates to the use of voltage biasing for the Josephson junctions, which provides several benefits. First, voltage biasing eliminates the need for biasing resistors as used in constant current mode devices. Such biasing resistors are known to be the dominant source of power dissipation in such logic circuits. Elimination of the biasing resistors thus reduce the power dissipation to the lowest possible value to that of the power dissipation of the switching devices themselves. In addition, the voltage biasing takes advantage of the voltage to frequency relationship of Josephson junctions and automatically establishes a global clock at the Josephson frequency without the need for extra circuitry; thus increasing the practical clock rate. In addition, elimination of extra clock circuitry increases the potential circuit density. The logic superconducting digital logic family in accordance with the present invention includes devices which perform logic functions such as, AND, OR etc. as well as non-logic functions, such as a shift register function.