The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 11, 2004

Filed:

Aug. 26, 2002
Applicant:
Inventors:

Theodore Van Duzer, El Cerrito, CA (US);

Xiaoxan Meng, El Cerrito, CA (US);

Nathan Newman, Scottsdale, AZ (US);

Lei Yu, Tempe, AZ (US);

Anupama Bhat Kaul, Pasadena, CA (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/906 ;
U.S. Cl.
CPC ...
H01L 2/906 ;
Abstract

A Josephson junction has inherent resistance which effectively shunts the junction and thereby obviates a separate shunt resistor and thus reduces surface area in an integrated circuit including a plurality of Josephson junctions. The Josephson junction comprises a stacked array of layers of Nb and a superconductor with T >9° K having a penetration depth greater than that of Nb, for example Nb Ti N, with a layer of a conducting material having a resistivity between 200 &mgr;&OHgr;-cm, 1 &OHgr;-cm, such as Ta N in the stack. The Josephson junction can be formed on a supporting substrate such as silicon with a ground plane such as Nb on the substrate and an insulating layer such as SiO separating the ground plane from the stacked array.


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