Halftone and error diffusion rendering circuits

Abstract

Circuits for rendering according to the present invention are operable to function in either halftone mode or error diffusion mode. A pixel multiplexor selects between a rasterized unrendered pixel signal from an input rasterized unrendered datastream in halftone mode and an error diffusion adjusted pixel signal generated by error diffusion hardware in error diffusion mode. A memory stores the current error diffusion state signal and retrieves it as the previous error diffusion state signal during the processing of the appropriate pixel in the next scan line in error diffusion mode. A threshold multiplexor selects between an error diffusion threshold signal and a halftone threshold signal. In halftone mode, the memory is operable to retrieve a halftone threshold signal which is supplied to the threshold multiplexor. A read address generator provides a read address signal to the memory for indicating the memory location from which to read either the previous error diffusion state signal or the halftone threshold signal. The read address generator includes a read address multiplexor for selecting between an error diffusion read address signal and a halftone read address signal. The read address generator further includes a stride multiplexor for providing the selected stride signal. The stride multiplexor has at least two stride inputs which receive stride signals corresponding to the appropriate stride values for error diffusion mode and halftone mode. A reset multiplexor provides the capability to set the read address signal either to a predetermined starting read address signal value or to the next read address signal.