The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 04, 2004
Filed:
Jun. 13, 2002
Kenneth Hass, Albuquerque, NM (US);
University of New Mexico, Albuquerque, NM (US);
Abstract
The back bias voltage on a functional circuit is controlled through a closed loop process. A delay element receives a clock pulse and produces a delay output. The delay element is advantageously constructed of the same materials as the functional circuit so that the aging and degradation of the delay element parallels the degradation of the functional circuit. As the delay element degrades, the transistor switching time increases, increasing the time delay of the delay output. An AND gate compares a clock pulse to an output pulse of the delay element, the AND output forming a control pulse. A duty cycle of the control pulse is determined by the delay time between the clock pulse and the delay element output. The control pulse is received at the input of a charge pump. The charge pump produces a back bias voltage which is then applied to the delay element and to the functional circuit. If the time delay produced by the delay element exceeds the optimal delay, the duty cycle of the control pulse is shortened, and the back bias voltage is lowered, thereby increasing the switching speed of the transistors in the delay element and reducing the time delay. If the throughput of the delay element is too fast, the duty cycle of the control pulse is lengthened, raising the back bias voltage produced by the charge pump. This, in turn, lowers the switching speed of the transistors in both the delay element and the functional circuit. The slower switching speed in the delay element increases time delay. In this manner, the switching speed of the delay element, and of the functional circuit, is maintained at a constant level over the life of the circuit.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile