The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 04, 2004

Filed:

Jan. 14, 2003
Applicant:
Inventor:

Yoshiki Sota, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ;
U.S. Cl.
CPC ...
H01L 2/348 ; H01L 2/352 ; H01L 2/940 ;
Abstract

A semiconductor package substrate of the present invention includes a first wiring substrate which has an opening section for mounting a semiconductor chip, and a second wiring substrate which has a second wire bonding terminal sections and second connecting terminal land sections, and through holes so that the second connecting terminal land sections on the first surface communicate to the second surface which is opposite to the first surface. The second surface of the first wiring substrate and the first surface of the second wiring substrate are mated in the state where the second wire bonding terminal sections are exposed. The semiconductor package substrate is suitable for a stacked semiconductor package, and capable of dense mounting. Also, it provides a stable and ensured mouting, thereby increasing the yield of the stacked semiconductor package.


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