Soi cell stability test method

Abstract

A method for testing SOI technology memory circuits, such as in SRAMs, for weak SOI cells, uses a reset test circuit with a wordline pulse width control circuit which can be implemented without performance impact and allows using unused silicon to minimize area usage impact and permits screening of integrated SOI memory array circuits for weak SOI cells using the test reset circuit to selectively change the wordline pulse width to a reduced time while the memory cell bit select and write signals turn off at normal times to stress the cell write margin. Further, during test, the word line pulse width can be extended by blocking the reset signal of the reset path test circuit to the word path to produce a longer than normal pulse width. In addition, during a test for normal operations the reset signal is allowed to pass through a pass gate multiplexer of the reset test circuit.