The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2004

Filed:

Aug. 14, 2001
Applicant:
Inventor:

Hiroshi Miura, Kyoto, JP;

Assignee:

Rohm Co., Ltd., Kyoto, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/328 ;
U.S. Cl.
CPC ...
G06F 1/328 ;
Abstract

A DMA controller has a cycle register in which the number of data transfer cycles to be performed in response to a single DMA transfer request is set, a cycle counter for counting the number of data transfer cycles actually performed, and a transfer counter for holding a value that is updated every time the number of data transfer cycles as held in the cycle register are completed. From the start to the end of the data transfer cycles, the number held in the cycle register is kept unchanged, and the data transfer cycles are performed until the value held in the transfer counter becomes equal to a predetermined value. In this configuration, even in a case where a predetermined number of DMA transfer cycles are performed in response to a single DMA transfer request and a plurality of DMA transfer requests are made in succession, the CPU has to set in the DMA controller only once the addresses of the source and destination locations and the values to be held in the cycle register and the transfer counter. This helps alleviate the burden on the CPU and thereby accordingly reduce the lowering of overall system performance.


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