Fractional-n frequency synthesizer with multiple clocks having different timings

Abstract

A frequency synthesizer device comprising a PLL circuit ( ) and a frequency-division ratio control circuit ( ). The PLL circuit ( ) includes a phase comparator ( ), a low-pass filter ( ), a voltage-controlled oscillator ( ), and a variable frequency divider ( ). The frequency-division ratio control circuit ( ) controls the variable frequency divider ( ) such that a frequency division ratio of the variable frequency divider ( ) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider ( ) and an output fdiv obtained via a delay element ( ) are used as clocks of an accumulator portion ( ) in the frequency-division ratio control circuit ( ). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit ( ) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.