The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2004

Filed:

Jun. 24, 1993
Applicant:
Inventors:

Thomas F. Knight, Belmont, MA (US);

David B. Salzman, New York, NY (US);

Assignee:

Polychip, Inc., Bethesda, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/11 ; H05K 7/06 ; H01L 2/348 ;
U.S. Cl.
CPC ...
H05K 1/11 ; H05K 7/06 ; H01L 2/348 ;
Abstract

Apparatus is described for capacitively signalling between different semiconductor chips and modules without the use of connectors, solder bumps, wire-bond interconnections or the like. Preferably, pairs of half-capacitor plates, one half located on each chip, module or substrate are used to capacitively couple signals from one chip, module or substrate to another. The use of plates relaxes the need for high precision alignment as well as reduces the area needed to effect signalling, and reduces or eliminates the requirements for exotic metallurgy.


Find Patent Forward Citations

Knight, Thomas. (2004). Method and apparatus for non-conductively interconnecting integrated circuits (U.S. Patent No. 6728113). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6728113

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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