The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2004
Filed:
Oct. 08, 2002
Applicant:
Inventors:
Douglas Brisbin, San Jose, CA (US);
Andy Strachan, Santa Clara, CA (US);
Assignee:
National Semiconductor Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/978 ;
U.S. Cl.
CPC ...
H01L 2/978 ;
Abstract
In a LDMOS transistor or matrix of transistors, hot carrier degradation effects are reduced by providing a ring drain and providing the ring drain with an overvoltage bias relative to the internal drain(s) of the LDMOS transistors.
Quick Actions:
Brisbin, Douglas. (2004). Method and device for improving hot carrier reliability of an ldmos transistor using drain ring over-drive bias (U.S. Patent No. 6727547). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6727547
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile