The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2004

Filed:

Jun. 10, 2002
Applicant:
Inventors:

Toshiyuki Nakamura, Tokyo, JP;

Hideaki Matsuhashi, Saitama, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/18236 ;
U.S. Cl.
CPC ...
H01L 2/18236 ;
Abstract

An FET is fabricated on an SOI substrate by the following processes. Openings are formed in laminated layers of a pad oxide film of about 5-10 nm and an oxidation-resistant nitride film of about 50-150 nm at positions where device isolation regions are to be provided. The substrate is irradiated by an ion implantation apparatus with at least one of Ar ions and Si ions with an implantation energy of 40-50 keV, and a dose of 1×10 to 5×10 cm . Field oxidation is then conducted to electrically separate adjacent devices. The regions of the substrate where the openings are formed become amorphous when irradiated, and the field oxidation is consequently enhanced. Hence, a thermal oxidation film having sufficient thickness can be obtained even at device isolation regions having isolation widths of 0.2 &mgr;m or less.


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