The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2004
Filed:
Dec. 06, 2001
Woo-Sik Kim, Kyunggi-do, KR;
Nae-In Lee, Seoul, KR;
Abstract
A method of forming a CMOS type semiconductor device having dual gate includes forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in first and second impurity type transistor regions, removing the first metal-containing layer and the first gate insulation layer in the second impurity type transistor region, forming a second gate insulation layer and a second metal-containing layer in the second impurity type transistor region, and forming first and second electrodes in the first and second impurity type transistor regions, respectively, by patterning the first and second metal-containing layers. When first and second impurities in the transistor regions are p-type and n-type impurities, respectively, a fermi level of the first metal-containing layer has an energy level similar to the valence band of the silicon layer in the first impurity type transistor region heavily doped by a p-type impurity, and a fermi level of the second metal-containing layer has an energy level similar to the conduction band of the silicon layer in the second impurity type transistor region heavily doped by an n-type impurity.