The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2004
Filed:
Oct. 04, 2000
Philip S. Homsinger, Poughkeepsie, NY (US);
Andrew D. Huber, Poughkeepsie, NY (US);
Debra K. Korejwa, Charlotte, VT (US);
William J. Livingstone, Underhill, VT (US);
Jeannie H. Panner, Underhill, NY (US);
Erich C. Schanzenbach, Dover Plains, NY (US);
Douglas W. Stout, Milton, VT (US);
Steven H. Voldman, South Burlington, VT (US);
Paul S. Zuchowski, Cambridge, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A integrated circuit (IC) chip with ESD robustness and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design. Array pads are wired to I/O cells located on the chip. Unused or floating pads may be tied to a power supply or ground line, either directly or through an electrostatic discharge (ESD) protect device. A multi-supply protect device (ESDxx) coupled between pairs of supplies and ground or to return lines is also included. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection. Robust ESD protection is afforded all chip pads. The design may then be verified.