Decoding circuit using path sequence including feed-back type path sequence storing blocks

Abstract

A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements to located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks ( ) to (D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements to are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits to . Each of the storing element block ( ) to (D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) ( ) to (D) outputted from a starting signal (pointer) generating circuit . A storing element block output circuit and storing element block output terminals ( ) to (D) are provided in each of the storing element blocks ( ) to (D) so that a path memory circuit output may be outputted through an OR circuit