The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2004
Filed:
Jan. 26, 2001
Applicant:
Inventor:
Masahiko Ishiwaki, Hyogo, JP;
Assignee:
Mitsubishi Denki Kabushiki Kaisha, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/309 ; G06F 7/52 ; G06F 7/72 ;
U.S. Cl.
CPC ...
H03M 1/309 ; G06F 7/52 ; G06F 7/72 ;
Abstract
A hold circuit holds results of processing in an arithmetic circuit collectively receiving four bits from inputs. The inventive arithmetic unit collectively processes an input data string, which has generally been processed bit by bit, by four bits at a time, whereby a CRC arithmetic operation can be speeded up. More preferably, the arithmetic unit can flexibly deal with change of a generating polynominal set in the arithmetic circuit when rendering set data corresponding to the generating polynomial changeable.
Ishiwaki, Masahiko. (2004). Arithmetic unit performing cyclic redundancy check at high speed (U.S. Patent No. 6725415). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6725415
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