The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2004
Filed:
Aug. 31, 2000
Applicant:
Inventor:
David Hartwell, Bolton, MA (US);
Assignee:
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/100 ; G06F 1/300 ; H03D 3/24 ;
U.S. Cl.
CPC ...
G06F 1/100 ; G06F 1/300 ; H03D 3/24 ;
Abstract
A phase-locked loop (PLL) circuit is used to synchronize data transfers between a fast clock and a slow clock domain. The data transfer can be deterministic, where the fast clocks are generated by a first PLL and the slow clocks are generated by a second PLL. The second PLL is used to create a phase relationship between the first PLL output clock and a third PLL output clock. The phase relationship can provide for a deterministic data transfer.