The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2004
Filed:
Mar. 27, 2003
Byungmoo Min, Lexington, MA (US);
Peter Kim, Cambridge, MA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus are arranged to provide an early comparison scheme for a pipelined ADC stage with a delay circuit. The pipelined ADC includes an amplifier that is biased by a precision bias circuit. The delay circuit includes inverting stages, where each inverting stage includes one or more current sources. The delay circuit is configured to provide a latch signal in response to a clocking signal for the pipelined ADC stage. The latch signal is utilized by one or more comparators for early evaluation of the output of the pipelined ADC stage. The current sources in the delay circuit may also be biased by the precision bias circuit such that variations in amplifier performance are tracked by variations in the performance of the delay circuit. Process, temperature, and power supply related variations in the timing may be minimized by the biasing arrangement of the amplifiers and the delay circuit.