The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Feb. 20, 2003
Applicant:
Inventors:

Masao Noro, Hamamatsu, JP;

Akihiko Toda, Hamamatsu, JP;

Assignee:

Yamaha Corporation, Hamamatsu, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 ;
U.S. Cl.
CPC ...
H03M 1/66 ;
Abstract

There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder , while the four less significant bits of the same are applied to a current addition circuit . The decoder selects one of FET's F to F based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r to r to be applied to an operational amplifier . On the other hand, switches to of the current addition circuit are switched, respectively, by the four less significant bits to turn respective FET's to on and off. As a result, currents flowing through turned-on ones of the FET's to are synthesized to flow through the resistor ra so that a voltage is generated across the resistor ra. The operational amplifier synthesizes the two voltages and then outputs the synthesized voltage. An FET and each of the FET's to form a current mirror circuit, whereby the influence of variations in characteristics of the resistors, etc. is eliminated.


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