The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Sep. 12, 2002
Applicant:
Inventors:

Ramsin M. Ziazadeh, San Jose, CA (US);

Jitendra Mohan, Santa Clara, CA (US);

Abu-Hena Mostafa Kamal, Santa Clara, CA (US);

Assignee:

National Semiconductor Corp., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/36 ;
U.S. Cl.
CPC ...
H03F 1/36 ;
Abstract

A circuit with low noise and reduced offset that feeds an input of an opamp with a programmable feedback resistor that provides variable gain settings. Input biasing currents are varied using control bits that are also used to adjust the gain. When the input signal is small (gain at higher setting), a minimum bias current is provided to source the input voltage swing. This scheme reduces the noise and offset generated by the lower transconductance of a biasing transistor while maintaining a constant SNR and fixed offset even in the presence of relatively small input swings. Also, when the input signal is large (gain at lower setting), a maximum bias current can be provided to accommodate the relatively large input swing level. Although the overall noise and offset current are increased for large input swings, the overall SNR and offset is maintained for relatively lower input swings.


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