The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Mar. 28, 2002
Applicant:
Inventors:

Juan-Antonio Carballo, Austin, TX (US);

David William Boerstler, Round Rock, TX (US);

Jeffrey L. Burns, Austin, TX (US);

Kevin John Nowka, Round Rock, TX (US);

Li Shi, Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/921 ; H03K 1/9177 ; H03K 3/356 ;
U.S. Cl.
CPC ...
H03K 1/921 ; H03K 1/9177 ; H03K 3/356 ;
Abstract

In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.


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