The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Nov. 18, 2002
Applicant:
Inventor:

King Tsu-Jae, Fremont, CA (US);

Assignee:

Progressant Technologies, Inc., Fremont, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/980 ;
U.S. Cl.
CPC ...
H01L 2/980 ;
Abstract

An improved MISFET is disclosed which is particularly suited as a replacement for conventional pull-up and load elements such as NDR diodes, passive resistors, and conventional FETs. The MISFET includes a charge trapping layer formed at or extremely near to an interface between a substrate (which can be silicon or SOI) and a gate insulation layer. In this fashion, charge traps can be optimized for extremely rapid trapping and de-trapping of charge because they are extremely close to a channel of hot carriers. The MISFET channel can be shut off during static operations to further reduce power dissipation, and can also be adapted to operate with negative differential resistance.


Find Patent Forward Citations

Tsu-Jae, King. (2004). Field effect transistor pull-up/load element (U.S. Patent No. 6724024). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6724024

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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