The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Aug. 17, 2001
Applicant:
Inventor:

Yong-Bae Kim, Cupertino, CA (US);

Assignee:

LSI Logic Corporation, Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ;
U.S. Cl.
CPC ...
H01L 2/1302 ;
Abstract

Removal of rough edges in punctured or ruptured pores on the walls of an opening, such as a via and/or trench opening, in a layer of porous dielectric material, in an integrated circuit structure, is carried out to permit satisfactory lining of all exposed surfaces of the porous dielectric material with a barrier layer which prevents contact between a copper filler and the porous dielectric material, and facilitates filling of the completely lined punctured/ruptured pore with such copper filler to eliminate void formation. The rough edges of the punctured/ruptured pores are removed by an isotropic etch of the exposed walls of the opening. Preferably, the dielectric material in the porous dielectric material is a low k dielectric material.


Find Patent Forward Citations

Loading…