The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 6723645 B1

PDF
Full Text
Expired
Date of Patent:
Apr. 20, 2004

Filed:

Jun. 06, 2001
Applicant:
Inventor:

Sung Gyu Pyo, Ichon-Shi, KR;

Assignee:

Hynix Semiconductor Inc, Kyungki-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 2/1302 ; H01L 2/13065 ; H01L 2/1311 ;
U.S. Cl.
CPC ...
H01L 2/1302 ; H01L 2/13065 ; H01L 2/1311 ;
Abstract

A method of forming a metal wiring in a semiconductor device is disclosed. In order to improve a low deposition speed in the process technology by which a damascene pattern of an ultra-fine structure is filled with copper by CVD method, a CECVD method is disclosed by which a chemical enhancer layer for increasing the deposition speed of copper is formed and the damascene pattern is then filled by means of MOCVD method using a copper precursor which forms a copper wiring. A diffusion prevention film is formed on the sidewall of the damascene pattern in the shape of a spacer in order to prevent an increase of the via resistance by the diffusion of copper into the sidewalls of the damascene pattern. A chemical enhancer layer is selectively formed on a lower metal layer that is exposed by the damascene pattern, thus allowing a selective partial filling of the damascene pattern. Therefore, copper filling in an ultra-fine structure is facilitated which also minimizes the electrical resistivity of the copper wiring.


Find Patent Forward Citations

Pyo, Sung. (2004). Method of forming a metal wiring in a semiconductor device (U.S. Patent No. 6723645). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/6723645

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