The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2004

Filed:

Dec. 31, 2002
Applicant:
Inventors:

Won-Ju Cho, Daejeon, KR;

Jong-Heon Yang, Daejeon, KR;

Moon-Gyu Jang, Daejeon, KR;

Seong-Jae Lee, Daejeon, KR;

Kyoung-Wan Park, Daejeon, KR;

Ki-Ju Im, Daejeon, KR;

Ji-Hun Oh, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 2/184 ; H01L 2/100 ;
U.S. Cl.
CPC ...
H01L 2/184 ; H01L 2/100 ;
Abstract

An ultra small-sized SOI MOSFET having a high integration density, low power consumption, but high performances, and a method of fabricating the same are provided. The method includes preparing a SOI substrate on which a monocrystalline silicon layer is formed, forming a first dielectric material layer doped with impurities of a first conductivity type on the SOI substrate, forming an opening to expose the monocrystalline silicon layer etching at least part of the first dielectric material layer, forming a channel region injecting impurities of a second conductivity type into the monocrystalline silicon layer exposed by the opening, forming a source region and a drain region in the monocrystalline silicon layer diffusing the impurities of the first dielectric material layer using heat treatment, forming a gate dielectric layer in the opening on the channel region, forming a gate electrode on the gate dielectric layer to fit in the opening, forming a second dielectric material layer on the entire surface of the SOI substrate on which the gate electrode is formed, forming contact holes to expose the gate electrode, the source region, and the drain region etching part of the second dielectric material layer, and forming metal interconnections to bury the contact holes.


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