The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2004
Filed:
May. 05, 2000
Ravi Subramanian, Mountain View, CA (US);
Infineon Technologies AG, Munich, DE;
Abstract
A digital wireless communication device comprises a software-programmable processor, a heterogeneous reconfigurable multiprocessing logic circuit, and a bus connecting the software-programmable processor and the heterogeneous reconfigurable multiprocessing logic circuit. The heterogeneous reconfigurable multiprocessing logic circuit comprises a set of heterogeneous signal processing kernels and a reconfigurable data router interconnecting the heterogeneous signal processing kernels. The software-programmable processor is selected from the group comprising: a digital signal processor and a central processing unit. The architecture provides the ability to reconfigure a single product platform for multiple standards, applications, services, and quality-of service, instead of developing multiple hardware platforms to establish the same collective functionality. The architecture also provides the ability to use software programming techniques to reduce product development time and achieve rapid and comprehensive product customization. The invention extends the performance efficiency of microprocessors and digital signal processors via the augmentation of data paths and control paths through a reconfigurable co-processing machine. The reconfigurability of the data path optimizes the performance of the data flow in the algorithms implemented on the processor.