Method and circuit arrangement for reading out and for storing binary memory cell signals

Abstract

The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair ( ), the binary memory cell signal from the memory tell is switched through via the bit line pair ( ) to at least one sense amplifier ( ), a binary output signal of the sense amplifier ( ) is switched through to a local data line pair ( ) as a binary intermediate signal, the binary intermediate signal on the local data line pair ( ) is switched through to at least one main data line pair ( ) by means of a main data line switching transistor pair ( ) in a manner dependent on a row control signal fed via a row control line ( ), the main data line switching transistor pair ( ) being arranged in the through-plating regions formed between the memory cell arrays.