The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2004

Filed:

Jun. 11, 2002
Applicant:
Inventors:

Andreas G. Andreou, Baltimore, MD (US);

Alyssa Apsel, Ithaca, NY (US);

Assignee:

Johns Hopkins University, Baltimore, MD (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/45 ;
U.S. Cl.
CPC ...
H03F 3/45 ;
Abstract

A low-power differential optical receiver useful for high-speed optical communication between CMOS chips includes a multi-stage differential amplifier circuit including a first differential transimpedance stage ( ) followed by a plurality of differential feed-forward, high-bandwidth gain stages ( ) and a final, differential-to-single-ended converter output stage ( ). The inputs of the transimpedance stage receive input signals from a MSM or PIN diode photo-detector. Transistors having plural, different threshold levels are employed within each differential amplifier stage to reduce the size of the footprint of the circuit and improve the gain and bandwidth while decreasing the parasitic capacitance. The optical receiver is fabricated on a silicon on insulator chip, such as in an ultra-thin silicon on sapphire CMOS process which enables the design of high speed circuits with low power consumption and no substrate cross-talk. The circuit design is well-suited for use in a multi-dimensional array of optical interconnects between CMOS chips or platforms.


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