The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2004

Filed:

Mar. 12, 2002
Applicant:
Inventors:

Kazuyoshi Nagase, Aichi-ken, JP;

Hiroshi Nomura, Nagoya, JP;

Assignee:

Denso Corporation, Kariya, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 ;
U.S. Cl.
CPC ...
G11C 7/00 ;
Abstract

A trimming circuit includes a signal separation circuit for separating an input signal into a clock signal, a reset signal, a data signal, and a memory writing voltage signal in accordance with voltage levels. The memory circuit in the trimming voltage control circuit has at least first and second different error correction circuits. The first error correction circuit has a higher error correction capability but lower input-per-output bit efficiency than the second error correction circuit to correct important data such as a highest bit inputted to a D/A converter. The second error correction circuit such as SEC has a higher input-per-output bit efficiency than the first error correction circuit to correct data with an error correction code. The lowest or second lowest input bits are directly supplied to the D/A converter without error correction.


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